(1) Field of the Invention
This invention relates to a display device and method, and more particularly to a display device and method for receiving and displaying image data on a display block.
(2) Description of the Related Art
In a display device, such as a liquid crystal display device, a method is sometimes employed in which one horizontal line on a liquid crystal panel is divided and scanned by a plurality of LCD (Liquid Crystal Display) drivers.
When scanning is performed by this method, it is required that transfer of image data to LCD drivers and scanning of one horizontal line on the liquid crystal panel are completed during one horizontal line period.
Recently, display devices have come to display an increasingly higher definition image. Accordingly, the amount of image data forming one horizontal line is ever increasing and one horizontal line period is also ever shortening. As a result, it has become necessary to complete transfer of image data to LCD drivers and scanning of one horizontal line in a short time period.
In line with the above recent trend, it is a conventional method employed for shortening a time period for transfer of image data to LCD drivers, to provide line memories for storing image data of one horizontal line and transfer portions of the image data therefrom to a plurality of LCD drivers, respectively, in a parallel fashion.
FIG. 6 shows an example of the construction of a liquid crystal display device based on the above method.
In the illustrated example, the liquid crystal display device is comprised of an I/F (Interface) 50, a control block 51, a left-side line memory 52, a right-side line memory 53, LCD drivers 56-1 to 56-6, and a liquid crystal panel 57.
The I/F 50 receives an image signal delivered, for instance, from a graphic accelerator, not shown, of a personal computer, not shown, extracts a CLK signal, horizontal and vertical synchronizing signals, and an image signal therefrom, and supplies these signals to the control block 51.
The control block 51 generates a driver control signal by dividing the frequency of the CLK signal by a factor of 2 to supply the driver control signal to the LCD drivers 56-1 to 56-6 and at the same time generates a left-side write enable signal and a right-side write enable signal from the horizontal and vertical synchronizing signals to supply these signals to the left-side line memory 52 and the right-side line memory 53, respectively. Further, the control block 51 supplies the image signal supplied from the I/F 50 in an amount corresponding to one horizontal line, to the left-side line memory 52 when the left-side write enable signal is active, and to the right-side line memory 53 when the right-side write enable signal is active.
The left-side line memory 52 stores image data which is supplied from the control block 51 and corresponds to a left half region of the one horizontal line.
The right-side line memory 53 stores image data which is supplied from the control block 51 and corresponds to a right half region of the one horizontal line.
The LCD drivers 56-1 to 56-3 cause image data supplied from the left-side line memory 52 to be displayed in the left half region of the one horizontal line on the liquid crystal panel 57.
The LCD drivers 56-4 to 56-6 cause image data supplied from the right-side line memory 53 to be displayed in the right half region of the one horizontal line on the liquid crystal panel 57.
The liquid crystal panel 57 displays an image corresponding to the image data supplied from the LCD drivers 56-1 to 56-6.
Next, the operation of the above conventional display device will be described.
Upon receiving the image signal, the I/F 50 extracts the CLK signal, the horizontal and vertical synchronizing signals, and the image signal therefrom, and supplies these signals to the control block 51.
The control block 51 generates the left-side write enable signal which becomes active for a left half region of one horizontal line, and the right-side write enable signal which becomes active for a right half region of the one horizontal line to supply the left-side and right-side write enable signals to the left-side line memory 52 and the right-side line memory 53, respectively.
Further, the control block 51 generates a driver control signal by dividing the frequency of the CLK signal by a factor of 2, and supplies the driver control signal to the LCD drivers 56-1 to 56-6.
Furthermore, the control block 51 supplies respective image signals as write data to the left-side line memory 52 and the right-side line memory 53.
The left-side line memory 52 reads in the write data for storage when the left-side write enable signal is active. As a result, image data corresponding to the left half region of the one horizontal line is stored in the left-side line memory 52.
On the other hand, the right-side line memory 53 reads in the write data for storage when the right-side write enable signal is active. As a result, image data corresponding to the right half region of the one horizontal line is stored in the right-side line memory 53.
It should be noted that since time periods during which the left-side and right-side write enable signals are active are identical, the same amount of image data is written in each of the left-side line memory 52 and the right-side line memory 53.
After storage of the image data in both of the left-side line memory 52 and the right-side line memory 53 has been completed, the left-side line memory 52 sequentially transfers the image data stored therein to the LCD drivers 56-1 to 56-3 in synchronism with a CLK signal (hereinafter referred to as “the frequency-divided clock signal”) which is obtained by dividing the frequency of the CLK signal supplied from the control block 51 by a factor of 2. More specifically, the left-side line memory 52 transmits a first portion of the image data to the LCD driver 56-1, then a second portion of the same to the LCD driver 56-2, and finally the remaining portion to the LCD driver 56-3.
At this time, similarly to the left-side line memory 52, the right-side line memory 53 as well sequentially transfers the image data stored therein to the LCD drivers 56-4 to 56-6 in synchronism with the frequency-divided clock signal. More specifically, the right-side line memory 53 transmits a first portion of the image data to the LCD driver 56-4, then a second portion of the same to the LCD driver 56-5, and finally the remaining portion to the LCD driver 56-6.
After the whole image data has been transferred to the LCD drivers 56-1 to 56-6 as described above, the control block 51 sends a control signal to each of the LCD drivers 56-1 to 56-6 for causing them to sequentially output the transferred image data to the liquid crystal panel 57. Responsive to the control signal, the LCD drivers 56-1 to 56-6 sequentially outputs the image data to the liquid crystal panel 57, whereby the scanning of one horizontal line is completed.
The above processing is repeatedly carried out for each horizontal line, and after completion of display of image data for all the horizontal lines, the next frame starts to be drawn.
According to the method described hereinabove, image data of one horizontal line is divided into two portions such that they are stored in the left-side line memory 52 and the right-side line memory 53, respectively, and transferred to the LCD drivers 56-1 to 56-3 and the LCD drivers 56-4 to 56-6 sequentially in a parallel fashion. Hence, assuming that a time period required for transfer of image data to be supplied to each LCD driver is constant, it is possible to reduce the frequency of a clock signal used in the transfer of image data to a half.
Now, in the conventional display device shown in FIG. 6, the number of the LCD drivers 56-1 to 56-6 is even (=6), and the left and right half regions of each horizontal line on the liquid crystal panel 57 are driven by the LCD drivers 56-1 to 56-3 and the LCD drivers 56-4 to 56-6, respectively. Accordingly, the amount of image data stored in the left-side line memory 52 and that of image data stored in the right-side line memory 53 are equal to each other.
However, as shown in FIG. 7, when the liquid crystal panel 57 is driven by an odd number of LCD drivers 56-1 to 56-7, and if the amount of image data stored in the left-side line memory 52 and that of image data stored in the right-side line memory 53 are different from each other, a time period required for transferring image data from the left-side line memory 52 to the LCD drivers 56-1 to 56-4 is longer than a time period required for transferring image data from the right-side line memory 53 to the LCD drivers 56-5 to 56-7.
Now, this problem will be described based on an example. Let it be assumed that as shown in FIG. 8, the left half region of the liquid crystal panel 57 is driven by the LCD drivers 56-1 to 56-3 each of which has 6 outputs, while the right half region of the liquid crystal panel 57 is driven by the LCD drivers 56-4 to 56-6 each of which has 6 outputs similarly to the LCD drivers 56-1 to 56-3.
If one data item is needed to obtain one output, and one pulse of the clock signal is necessary for transfer one data item, 18 (=6×3) pulses of the frequency-divided clock signal are necessitated to transmit image data from the left-side line memory 52 to the LCD drivers 56-1 to 56-3. The same applies to a case in which image data is transferred from the right-side line memory 53 to the LCD drivers 56-4 to 56-6.
Next, a case illustrated in FIG. 9 will be considered in which the number of the LCD drivers 56-1 to 56-7 is odd. In this example, it is necessary to transfer image data from the left-side line memory 52 to the LCD drivers 56-1 to 56-4, and also image data from the right-side line memory 53 to the LCD drivers 56-5 to 56-7. Here, to transmit image data from the left-side line memory 52 to the LCD drivers 56-1 to 56-4, 24 (=6×4) pulses of the frequency-divided clock signal are necessary, while to transmit image data from the right-side line memory 53 to the LCD drivers 56-5 to 56-7, 18 (=6×3) pulses of the frequency-divided clock signal are necessary.
By the way, the frequency-divided clock signal is generated by dividing the frequency of the CLK signal delivered from the I/F 50 by a factor of 2, while the number of pulses of the CLK signal during one horizontal time period is set based on the number “42” (=6×7) of image data items which should form one horizontal line. If the number of pulses of the CLK signal during the one horizontal time period is equal to 42, the number of pulses of the frequency-divided clock signal which is formed by dividing the frequency of the CLK signal by a factor of 2, during the one horizontal time period becomes equal to “21” (=42÷2). Although this number of pulses is sufficient for 18 pulses necessary for transfer of image data from the right-side line memory 53 to the LCD drivers 56-5 to 56-7, it is not sufficient for 24 pulses necessary for transfer of image data from the left-side line memory 52 to the LCD drivers 56-1 to 56-4. As a result, in this case, the transfer of data to the left side of the liquid crystal panel 57 cannot be carried out in time.
Further, since LCD drivers are generally provided as semiconductor devices, the number of outputs thereof is usually predetermined. Therefore, if the number of outputs of a single LCD driver and the number of pixels of the liquid crystal panel 57 do not have the relationship of an integral multiple between them, LCD drivers sometimes have extra outputs which are a surplus as in a case illustrated in FIG. 10. In the illustrated example, the leftmost LCD driver 56-1 and the rightmost driver 56-6 each have two extra outputs.
Now, LCD drivers are each required to have a control signal input thereto after reading in data corresponding to the number of outputs thereof, so that as shown in FIG. 10, even when there are extra outputs among the LCD drivers, it is necessary to input data corresponding to the number of outputs which each LDC driver inherently has, to each LCD driver. In other words, even when an LCD driver has extra outputs, the LCD driver is required to be supplied with the same number of pulses of the clock signal as supplied when it has no extra outputs. Accordingly, in the illustrated example, 18 pulses of the clock signal are required although the number of image data items output to the liquid crystal panel 57 is 16 on each of the left and right sides of the liquid crystal panel 57.
Therefore, when the number of pulses of the CLK signal is set according to the number of pixels of one horizontal line on the liquid crystal panel 57, there sometimes occurs the same problem as described above.
Furthermore, as shown in FIG. 11, a signal (gate turn-ON signal: see FIG. 11(A)) by which each LCD driver turns on a gate of the liquid crystal panel 57, and a liquid crystal voltage-applying signal (see FIG. 11(B)) for writing image data in the liquid crystal panel 57 have the relationship shown in these figures between the same.
FIG. 12 is a diagram showing an equivalent circuit of the liquid crystal panel. As shown in the figure, a liquid crystal panel 5 is comprised of a gate bus line 1, a data bus line 2, a TFT (Thin Film Transistor) 3, and a liquid crystal capacitance 4. The gate turn-ON signal shown in FIG. 11(A) is applied to the gate bus line 1, while the liquid crystal voltage-applying signal shown in FIG. 11(B) is applied to the data bus line 2. When these voltages are applied, the TFT 3 is brought into conduction, whereby a predetermined voltage is applied to the liquid crystal capacitance 4.
Here, a time period Tdh from a time the gate turn-ON signal has become active to a time the LCD driver starts writing image data in the liquid crystal panel 57 cannot be set to be shorter than a certain fixed time period, and hence the display device is designed such that the time period Tdh is fixed in a manner adjusted to a CLK signal having the maximum frequency that can be input. Therefore, if a CLK signal is input which has a lower frequency than the maximum frequency, the time period Tdh is made longer. Since one horizontal time period Th is fixed, if the time period Tdh is prolonged, a liquid crystal write time period is shortened accordingly. This makes it impossible to ensure a sufficient write time for writing image data in the liquid crystal panel 57.